CMOS pseudo-NMOS programmable capacitance time vernier system and method for controlled delay of timing edges

摘要

An integrated circuit system having integrated thereon, one or more time vernier subsystems (106,108,110) for fine tuning coarse timing edges of corresponding input signals (103). The system comprises means for generating a control signal for each input signal (103) to specify the amount of fine tuning, and at least one time vernier subsystem having a first input to receive the control signal (112) and a second input to receive a corresponding input signal (103), and means for fine tuning the coarse edges of the corresponding input signal according to the specified amount of fine tuning and for outputting the result.