Semiconductor memory devices including precharge control circuitry to prevent digit line pairs from being precharged after replacement with redundant digit line pairs

摘要

PURPOSE:To prevent an abnormal leak current which flows through a defective bit line. CONSTITUTION:Gates of precharge transistors Q1 and Q2, which configure loading circuits of bit lines D and the inverse of D, and an equalizer transistor Q3 are connected to a ground level through a high resistance element R1 and furthermore, these gates are connected to a precharge signal source through a fuse F1. When these are replaced by a redundant cell, the fuse F1 is cut and no charge is supplied to the defective bit lines D and the inverse of D and if there is an abnormal leak path in defective lines, no current flows.