A jitter correction circuit is circuit for suppressing a jitter contained in a reproduced digital signal. This jitter correction circuit comprises a phase-locked loop circuit comprising a phase comparing circuit (9), a second low-pass filter (10), a second voltage control oscillator (11) and a second frequency dividing circuit (12). The phase-locked loop circuit provides an oscillation output which causes little influence to a jitter component contained in a reproduced signal digitally converted by an analog-to-digital converting circuit (1). The digitally converted reproduced signal is resampled in a sampling pulse generating circuit (13) and a resampling circuit (7) which operates based on the above stated phase-locked loop circuit. As a result, the resampling circuit (7) provides an output having a considerably decreased amount of jitter.
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