Dynamic multi-mode parallel processor array design computer system

摘要

The parallel RISC computer system can be extended to more widely located processing elements through an interconnection network that combines multiple processors capable of MIND mode processing with each other as broadcasts of instructions to selected groups of units controlled by the controlling processor. An example illustrating a tightly coupled VLSI embodiment as a design is provided by a multi-mode dynamic multi-mode parallel processor array. The combination of processing element logic enables dynamic mode assignment and dynamic mode switching, while allowing a processor to operate in SIMD mode to make maximum memory and cycle time usage. In instruction by the instruction level basis, the mode is the original sequence that allows the programmer or compiler to create a program for a computer system using SIMD to MIND, and the best kind of parallax (SISD, SIMD, MIND). It can even be switched to the SISD mode on the controlling processor for computational purposes. Moreover, in the SIMD mode the performance in particular can be set up to run the application in the limitation of the memory cycle time. As an ALLNODE switch and alternative path, the system can be made dynamically in a few cycles for many processors. Each processing element and memory has a MIND capability in which the processor's indication registers, condition registers and program counters provide common resources used in MIND and SIMD. The program counter becomes the base register in SIMD mode.;In one embodiment all the indicator registers are combined to form a common broadcast path, and in alternative embodiments, the ALLNODE switch is an alternative path for broadcast to all processors coupled by an interconnection network to be selected as the system of choice. It is used as.