Parallel processor with instruction cache and buffer register - uses simplified logic for cancellation of cache instructions at addresses shifted by more than four words

摘要

The superscalar processor fetches and executes several instructions simultaneously for distribution to corresp. functional units. It operates with availability flag registers (20a-20d) relating to instructions (IR1-IR4) stored in an instruction register (12) in the foregoing stage of an instruciton decoder (13). Flags (ia1-ia4) are controlled according to misalignment information concerning the deg. to which an address in the cache (1) is shifted w.r.t. a four-word limit. Such instructions are cancelled logically without provision of a reset function in the register (12). ADVANTAGE - Fewer transistors used, reduced cycle time by using latch circuit as instruction register.