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Monolithic digital phaselock loop circuit having an expanded pull- in range
Monolithic digital phaselock loop circuit having an expanded pull- in range
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机译:具有扩展吸入范围的单片数字锁相环电路
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摘要
A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a VCO to compensate for process induced variations in the VCO natural frequency and to extend the pull-in range by .+-.50% of the frequency of a reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up- down counters, one to control the phase; the other, the frequency; a first one-shot circuit that drives the phase up-down counter to detect every level transition of the reference clock and a second one-shot circuit that drives the frequency up-down counter to provide a pulse for every falling edge of the reference clock; and a shift register responsive to the phase comparator to store the value of the phase comparator thereby providing indication of a frequency lock between the reference clock and the VCO.
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