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Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families

机译:发射极发射极逻辑(EEL)和发射极点集逻辑(ECDL)系列

摘要

Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.
机译:公开了逻辑单元,其由高速逻辑门的阵列组成,其高速逻辑门的输出连接在一起并耦合至低功率驱动器。通过使用非常快的逻辑门来实现高速和开关速率,这些逻辑门没有增益,并且利用有线逻辑功能来实现两个逻辑级别,而无需增加通过另一个逻辑门的传播延迟。这些逻辑门阵列耦合到驱动器,这些驱动器恢复逻辑电平并提供驱动互连电容所需的功率,同时在此过程中消耗并消耗最少的功率。另一个逻辑电路公开了逻辑门阵列,作为到另一个逻辑门的输入,各个门由砷化镓成分组成,并且在每个门的输出级中内置有驱动器。

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