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Method for forming PN junction isolation regions by forming buried regions of doped polycrystalline or amorphous semiconductor

机译:通过形成掺杂的多晶或非晶半导体的掩埋区来形成PN结隔离区的方法

摘要

In a semiconductor device having island regions formed in a surface area of a substrate, the island regions are electrically isolated from the substrate via buried regions formed of polycrystalline or amorphous semiconductor, without use of epitaxial growth technique. Since the polycrystalline or amorphous semiconductor includes a great number of recombination centers, parasitic operation between the elements formed on the semiconductor substrate can be prevented. Further, the buries regions are excellent in heat conductivity, the breakdown resistance against surge voltages or static electricity can be improved. Furthermore, when applied to a CMOS, it is possible to prevent latch up action caused by a parasitic thyristor formed in the CMOS, by the presence of the buried regions including a great number of recombination centers.
机译:在具有在衬底的表面区域中形成的岛区域的半导体器件中,岛区域通过由多晶或非晶半导体形成的掩埋区与衬底电隔离,而不使用外延生长技术。由于多晶或非晶半导体包括大量的复合中心,因此可以防止在半导体衬底上形成的元件之间的寄生操作。此外,掩埋区域的导热性优异,可以提高对浪涌电压或静电的耐击穿性。此外,当应用于CMOS时,由于包括大量复合中心的掩埋区的存在,可以防止由在CMOS中形成的寄生晶闸管引起的闩锁作用。

著录项

  • 公开/公告号US5212109A

    专利类型

  • 公开/公告日1993-05-18

    原文格式PDF

  • 申请/专利权人 NISSAN MOTOR CO. LTD.;

    申请/专利号US19910762264

  • 发明设计人 TERUYOSHI MIHARA;

    申请日1991-09-20

  • 分类号H01L21/76;

  • 国家 US

  • 入库时间 2022-08-22 04:58:21

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