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Hardware bit block transfer operator in a graphics rendering processor

机译:图形渲染处理器中的硬件位块传输运算符

摘要

A hardware bit block transfer operator for transferring blocks of data from a source address to a destination address in a display memory, a bit mapped memory, or a host processor, or between the two source and destination addresses in a graphics rendering cogenerator. Functionally, blocks to be transferred are addressable to the bit level thus requiring shifting and reformatting from the source word to the destination word alignment. The cogenerator automatically identifies all required boundary exceptions and applies the appropriate sequencing at the proper time during the block transfer operation. All that the programmer is required to provide are definitions of color depth, source transparency address, source start address, destination transparency address and destination window. The proper transfer is then performed by the cogenerator with a single command to the transfer operator.
机译:硬件位块传输运算符,用于将数据块从源地址传输到显示存储器,位映射存储器或主机处理器中的图形地址,或者在图形渲染生成器中的两个源地址和目标地址之间传输。在功能上,要传输的块可寻址到位级别,因此需要从源字到目标字对齐的移位和重新格式化。协同生成器自动识别所有必需的边界异常,并在块传输操作期间的适当时间应用适当的排序。程序员只需要提供色深,源透明地址,源起始地址,目标透明地址和目标窗口的定义即可。然后由热电发电机以单个命令执行适当的传输给传输运算符。

著录项

  • 公开/公告号US5218674A

    专利类型

  • 公开/公告日1993-06-08

    原文格式PDF

  • 申请/专利权人 HUGHES AIRCRAFT COMPANY;

    申请/专利号US19900582694

  • 发明设计人 JOHN M. PEASLEE;JEFFREY C. MALACARNE;

    申请日1990-09-14

  • 分类号G06F15/00;G06F15/20;

  • 国家 US

  • 入库时间 2022-08-22 04:58:14

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