Random access memory device having transfer gate unit for blocking flash write data buffer unit from parasitic capacitance coupled with bit line pairs of memory cells

摘要

A dynamic random access memory device enters a flash write phase of operation for writing a flash write data bit into a plurality of random access memory cells, and the flash write data bit is transferred from a flash write data buffer unit through a transfer gate unit, a set of bit line pairs respectively coupled with sense amplifier circuits, another transfer gate unit and another set of bit line pairs coupled with a random access memory cell array, wherein another transfer gate unit blocks the flash write data buffer unit and the sense amplifier circuits from parasitic capacitances coupled with another set of bit line pairs so that the flash write data buffer unit with small current driving capability rapidly produces small differential voltage levels indicative of the flash write data bit on the bit line pairs coupled with the sense amplifier circuits.