PURPOSE:To attain digital transmission at a high speed, to contrive to reduce a scale, and to decrease power consumption by inputting the whole or a part of a latch output of N bits, detecting a synchronizing signal, and executing a selection control of N pieces, based on a result of detection. CONSTITUTION:A digital signal which is inputted to a shift register 1 of N bits is developed to N bits and supplied to a selector 3, and the selector 3 selects one of inputs of N bits and supplies it to a series input of a shift register 2. By such selection control, an appropriate phase can be selected from in N pieces of phases. A latch 4 latches an N-bit data which is developed by an N frequency division output 51 of a transmission clock 9 from a counter 5. This latch output is supplied to a receiving part 7, and also, inputted to a synchronization detecting circuit 6. The synchronization detecting circuit 6 monitors this developed output, controls the selector 3 by a control signal 61, and provides an optimum phase.
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