LAYOUT COMPACTION METHOD FOR LARGE SCALE ANALOG INTEGRATED CIRCUIT

摘要

PURPOSE: To reduce a wiring area by expressing the initial arrangement and wiring of elements as a prescribed graph and deciding the detailed arrangement and wiring reducing invalid areas by performing compaction while keeping this graph. ;CONSTITUTION: In the layout pattern of an analog LSI, K1, K2, K4, K5 and K6 denote an element node, external terminal node, via node, branch point node and cross point node respectively. First of all, the initial arrangement and processing wiring of elements are expressed as a planar graph, a distance from the right outside terminal node is calculated concerning all the nodes, an arrangement valve initially sets border lines and decides the detailed coordinates of nodes selected from the planar graph, and arranged and wired areas and initially arranged and wired areas are updated. Then, the detailed arrangement and wiring reducing the invalid areas is decided by performing the compaction by successively moving the nodes while keeping the graph and paying attention from the node existent at the prescribed position in the graph.;COPYRIGHT: (C)1994,JPO&Japio