首页> 外国专利> LOGICAL CIRCUIT GROUP WITH SELF-TIMING FUNCTION WHICH IS PERFECT IN TERMS OF FUNCTION

LOGICAL CIRCUIT GROUP WITH SELF-TIMING FUNCTION WHICH IS PERFECT IN TERMS OF FUNCTION

机译:具有自整定功能的逻辑电路组,在功能方面具有完善的功能

摘要

PURPOSE: To provide a logical circuit group with a self-timing function, which is perfect in terms of a function. ;CONSTITUTION: This logical system uses a new mouse trap logical gate(MLG) 100 executing a new vector logic. In a vector logical system, the valid vector logical state(VVS) of an optional number and the invalid vector logical state(IVS) of 1 are defined by a logical signals on a set of logical paths. When all the logical paths show low-level logical signal, IVS is defined. In addition VVS is defined when only one of the logical paths shows a high-level logical signal. In addition MLG 100 directly connectable in series and/or in parallel executes the logical mechanism. Each MLG 100 is provided with operation preparing mechanisms 108, 118 and 128, ladder logical parts 110, 120 and 130, and buffers 112, 122 and 132.;COPYRIGHT: (C)1994,JPO
机译:目的:为逻辑电路组提供自定时功能,这在功能上是完美的。 ;构成:该逻辑系统使用执行新矢量逻辑的新鼠标陷阱逻辑门(MLG)100。在矢量逻辑系统中,可选逻辑的有效矢量逻辑状态(VVS)和无效矢量逻辑状态(IVS)为1由一组逻辑路径上的逻辑信号定义。当所有逻辑路径均显示低电平逻辑信号时,将定义IVS。另外,当仅逻辑路径之一显示高级逻辑信号时,将定义VVS。另外,可直接串联和/或并联连接的MLG 100执行逻辑机制。每个MLG 100配备有操作准备机构108、118和128,梯形逻辑部分110、120和130以及缓冲器112、122和132 。;版权所有:(C)1994,JPO

著录项

  • 公开/公告号JPH06236254A

    专利类型

  • 公开/公告日1994-08-23

    原文格式PDF

  • 申请/专利权人 HEWLETT PACKARD CO HP;

    申请/专利号JP19920093064

  • 发明设计人 YETTER JEFFRY D;

    申请日1992-04-13

  • 分类号G06F7/38;

  • 国家 JP

  • 入库时间 2022-08-22 04:51:28

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