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MULTILEVEL LOGIC OPTIMIZING DEVICE

机译:多级逻辑优化设备

摘要

PURPOSE: To reduce the circuit area and to increase the calculation speed by determining an optimum factor in consideration of not only the area cost of the factor itself and the delay cost but also the wiring cost. ;CONSTITUTION: A factor candidate enumerating means 2 enumerates factor candidates of an object circuit. An area candidate calculating means 3 and a delay cost calculating means 4 calculate area costs and delay costs of these factor candidates by constraint conditions. A wiring cost calculating means 5 calculates the fan-out number of each factor by a fan-out number calculating means, and a wiring area cost calculating means calculates the area cost of wiring based on this fan-out number in accordance with a calculation formula preliminarily estimated for each technology, and a wiring delay cost calculating means calculates the delay cost of wiring in the same manner. A wiring cost adding means adds these costs related to wiring to costs obtained by the area cost calculating means 3 and the delay cost calculating means 4 to calculate the total cost. A factor determining means 6 selects and determines one having the optimum total cost out of factor candidates.;COPYRIGHT: (C)1993,JPO&Japio
机译:目的:通过确定最佳因素来减少电路面积并提高计算速度,不仅要考虑因素本身的面积成本和延迟成本,还要考虑布线成本。 ;组成:因子候选者枚举装置2枚举目标电路的因子候选者。区域候选者计算装置3和延迟成本计算装置4通过约束条件计算这些因子候选者的区域成本和延迟成本。布线成本算出单元5通过扇出数计算单元算出各要素的扇出数,布线面积成本算出单元根据该算出式,根据计算式算出布线的面积成本。预先对每种技术进行估计,布线延迟成本计算装置以相同的方式计算布线的延迟成本。布线成本增加装置将与布线有关的这些成本加到由面积成本计算装置3和延迟成本计算装置4获得的成本上,以计算总成本。要素确定装置6从要素候选中选择并确定具有最佳总成本的要素。版权:(C)1993,JPO&Japio

著录项

  • 公开/公告号JPH05342302A

    专利类型

  • 公开/公告日1993-12-24

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP19920153742

  • 发明设计人 MAEDA NAOTAKA;

    申请日1992-06-12

  • 分类号G06F15/60;

  • 国家 JP

  • 入库时间 2022-08-22 04:47:07

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