Static edgetriggered D flip-flop with a low power consumptions

摘要

A static, edgetriggered, D flip-flop has the second (feedback) inverter of each latch of the flip-flop structure formed by four field effect, complementary-by-pair, transistors (MP1, MN1, MP2, MN2), functionally connected in series between the supply nodes. A first pair of complementary transistors (MP2, MN2) having a source connected to one and the other supply nodes, respectively, have a gate which is connected to the supply node of opposite sign as referred to the sign of the supply node to which the respective source is connected. The other pair of complementary transistors (MP1,MN1) Have their drain connected in common to the output node (A) of the inverter, a gate connected to the output node of the first (forward) inverter (I) of the latch, and a size which is essentially smaller than the size of said first pair of complementary transistors (MP2, MN2). IMAGE