Computation in graph reduction machines for performing lazy graph reduction includes repeatedly re-writing a graph until a final result is obtained. For this pupose memory is divided into heap and stack sections which are frequently accessed causing a bottleneck since data trasfer is controlled by a CPU and passes by way of a single data bus. This problem is addressed by using a plurality of modules (13, 14, 16, 17) each comprising a section of heap or stack memory, and ALU and a hinge (switch means) for coupling the memory section to a network of system buses (15) or a VLIW instruction memory (21, 22, 23). Data transfer between the heap and stack can then be carried out in parallal without involving a global processing unit (20) which performs all those conventional computing operations not involving data transfer and also controls operation of the whole program stored by the VLIW memory. In general, the architecture is especially suitable for instruction level parallelism where many instructions relate to memory operations.
展开▼
