A CMOS output buffer (10) includes a transient pull-up circuit (14), a transient pull-down circuit (16) and a keeper circuit (12). The pull-up circuit (14) is responsive to a high drive enable pulse signal (HENB) for generating a transition from a low logic level to a high logic level at an output node (W). The pull-down circuit (16) is responsive to a low drive enable pulse signal (LENB) for generating a transition from the high logic level to the low logic level at the output node (W). The keeper circuit (12) is responsive to the high and low drive enable pulse signals (HENB, LENB) so as to maintain the output node (W) at the high logic level after the output node (W) has made the low-to-high transition and to maintain the output node (W) at the low logic level after the output node (W) has made the high-to-low transition. The CMOS output buffer (10) has a high speed of operation and has a high immunity to noise.
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