首页>
外国专利>
Hierarchical memory system for microcode and means for correcting errors in the microcode
Hierarchical memory system for microcode and means for correcting errors in the microcode
展开▼
机译:用于微代码的分层存储系统以及用于纠正微代码中的错误的装置
展开▼
页面导航
摘要
著录项
相似文献
摘要
The invention comprises a hierarchical memory system for storing microinstructions with a main memory (10) connected through a memory bus (60) to secondary memory (70). The secondary memory (70) is divided into an area (90) for storing performance critical microinstructions containing microinstructions permanently stored in said secondary memory (70) and an area (80) for storing transient microinstructions which may be paged into the secondary memory (70) from the main memory (10) as required. Means (120, 180, 190) are provided which detect whether the microinstruction being decoded in a microinstruction decoder (130) is the correct microinstruction or has a parity error. On detection of an erroneous microinstruction, the microinstruction is reloaded from the main memory (10) into the microinstruction memory (70) and then passed to the microinstruction decoder (130).;The hierarchical memory system finds particular application in a multi-processor system in which with each processor is associated one secondary memory (70) and one main memory (10) is provided for the multi-processor system.
展开▼