Apparatus and method for improving cache consistency using a single copy of cache tag memory in a multiprocessor computer system

摘要

In a multiprocessor computer system, an apparatus and method for a cache controller is disclosed that maintains cache coherency in the structure of a cache memory having a single copy of a cache tag while supporting multiple good operations. The CPU includes a small internal cache memory structure.;Almost large external cache arrays are coupled to the CC via the CPU and the primary integrated address and databus.;The CC is in turn coupled to a second bus that interconnects with the processor, the I / O device, and the main memory, among other devices. The external cache is subblocked. The CC's cache directory tracks the use of external caches. The input buffer of the CC is connected to a first bus that provides buffering of instructions sent by the CPUs. The output buffer of the CC is coupled to the second bus to buffer the instructions indicated by the CC with the device operating on the second bus.;The virtual bus interface (VBI) receives an entry formed in the input buffer, thus reducing the input buffer to accept other commands. The cache invalidation queue (CIQ) register stores the address of the cache subblock that goes to the import invalidation operation. The address of the destination device is also read into the output buffer. If the address of the destination device stored in the output buffer matches the address of the CIQ register, the CC issues a read-invalidate instruction and the invalid block of the cache is filled with the data corresponding to the priority-access processor. Override intervening redundancy issued by the CPU accessing. Response times for roaming requests are bound and data consistency between cache and handler is preserved.