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Apparatus and method for improving cache consistency using a single copy of cache tag memory in a multiprocessor computer system
Apparatus and method for improving cache consistency using a single copy of cache tag memory in a multiprocessor computer system
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机译:用于在多处理器计算机系统中使用高速缓存标签存储器的单个副本来提高高速缓存一致性的设备和方法
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摘要
In a multiprocessor computer system, an apparatus and method for a cache controller is disclosed that maintains cache coherency in the structure of a cache memory having a single copy of a cache tag while supporting multiple good operations. The CPU includes a small internal cache memory structure.;Almost large external cache arrays are coupled to the CC via the CPU and the primary integrated address and databus.;The CC is in turn coupled to a second bus that interconnects the processor, the I / O device, and the main memory, among other devices. The external cache is subblocked. The CC's cache directory tracks the use of external caches. The input buffer of the CC is connected to a first bus that provides buffering of instructions sent by the CPUs. The output buffer of the CC is a device that operates on the second bus and is coupled to the second bus to buffer the instructions indicated by the CC.;The virtual bus interface (VBI) receives an entry formed in the input buffer, thus reducing the input buffer to accept other commands. The cache invalidation queue (CIQ) register stores the address of the cache subblock that goes to the import invalidation operation. The address of the destination device is also read into the output buffer. If the address of the destination device stored in the output buffer matches the address of the CIQ register, the CC has issued a read-invalidate instruction and the invalid block of the cache is filled with the data corresponding to the priority-access processor. Override intervening redundancy issued by the CPU accessing. The response time for roaming requests is bound and preserves data consistency between cache and handler.
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