Parallel register transfer mechanism for a reduction processor for carrying out of programs are stored in the form of a binary graph and the use of languages codes without variable use.

摘要

A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result is obtained. A register file is provided with several crossbar networks interconnecting the various registers in the file for simultaneous transfer of their contents.