Procedures for the inclusion of time parameters in the synthesis of logical circuit designs.

摘要

During the synthesis of a logic circuit in which a plurality circuit components are examined and, in the presence of certain criteria, are changed in accordance with preestablished rules, timing parameters are estimated for selected circuit locations. Forward timing delays are determined by adding the timing delays associated with the intervening circuit components and media paths between an input terminal or latch component output terminals and a successive locations on the signal path. Similarly, a derived budget timing delay constant is calculated by designating a budget or design delay at any location in the circuit and by subtracting timing delays asssociated with the intervening components between that location and the previous location along the signal path in the reverse direction. The derived budget timing delay constant is substracted from the forward timing delay at each selected location to derive a timing debt for each selected location. The timing debt can be used as a criterion to determine when the implementation of circuit component should be changed. The timing information is stored in data structures associated with terminals of components and can include data with respect to a multiplicity of designated paths for complex circuits for which examination of all signal paths requires a prohibitive amount of time, the technique can be used between groups of latches that are activated by timing signals having known signal delays. The resulting timing data can be derived and stored for all latch (input signal and output signal) paths affecting each selected location.