Synchronisation circuit for decentralised counters - uses control clock source controlling synchronisation signal source providing individual signal for each decentralised counter

摘要

The synchronisation circuit allows a number of decentralised counters (D21...D23) within respective communications devices to be synchronised with a master count clock provided by a central clock source (Z). The latter controls a programmable synchronisation signal source (FMG) providing individual synchronisation signals (FMB1...FMB3) for each of the decentralised counters, which have identical synchronisation stages (SYN1...SYN3). Pref. each decentralised counter has a test word generator supplying a signal to a central test receiver at which it is evaluated to control the delivery of the individual synchronisation signal. USE/ADVANTAGE - In telephone exchange, e.g. for metering. Can work in parallel, independently or as part of counter chain. Incorporates function testing of individual decentralised counter synchronisation stages.