Phase control for quartz clock motor - feeds synchronisation pulses from oscillator to counter and motor speed pulses to second counter, providing control variable via comparator

摘要

Synchronisation pulses from a reference quartz oscillator are counted by a first binary counter, and motor pulses, proportional to its speed, are counted by a second binary counter, and both counter readings are compared by a digital comparator. Output signal of the latter together with those from last stages of the counters control through a logic circuit the switching of a variable controlling the speed, so that when a counter capacity is overrun, the logic circuit output signal is inverted.