Multiple memory with identical units on common system bus - contains bus address control circuits for switching between master and back=up units on deflection of fault in master unit

摘要

Each of the identical storage units (e.g. 1,101) contains a refresh request circuit (4,104), a bus control circuit (3,103), a bus address circuit (2,102) and a one/two-bit readout error detection circuit (7,107). A master refresh request circuit delivers a memory refresh command using the bus clock, and a back-up refresh request circuit does the same using a trigger signal from the main memory. A master bus control circuit addresses the system bus, and a back-up bus control circuit inhibits addressing of the master unit. ADVANTAGE - Both synchronous and parallel operation between storage units can be maintained without interruption in the event of different errors or breakdowns in main storage.