Processor module of a fault tolerant computer, and cache flush system therein

摘要

A processor module of a fault tolerant computer which executes a cache flush operation at high speed and has a real time characteristic is equipped with a cache memory 1908, counter 402 and timer 4. The entry address of any updated cache block within the cache memory is stored in a stack 401. A cache flush is effected by reference to the entry address in the stack when at least one recovery point setting condition is satisfied. A main memory has paired memory modules each of the same storage physical space and equipped with a buffer memory, so that a cache block is simultaneously transferred to a pair of buffer memories in the flush operation. The recovery-point setting conditions are that (a) the number of non-updated cache blocks in a cache line reaches a given value, (b) the total number of updated cache blocks in memory 3 reaches a given value, and (c) that (a) and (b) do not occur within a given time period. IMAGE