Diophantine synthesizer

摘要

A frequency synthesizer with at least two main Phase Locked Loops (PLLs) and a signal combiner, where each PLL's input is driven by a reference source of frequency F.sub.refj, and each PLL has programmable dividers in both its input path (M and P) and its feedback path (N and Q). The synthesizer utilizes a method to produce an output frequency F.sub. out that is a close approximation to a requested frequency F.sub.req. The method includes making a series of rational fraction approximations .sup. X i/Y.sub.i to the ratio .sup.F req/F.sub.refj, factoring the resulting Y. sub.i 's into several factors M.sub.i and P.sub.i, picking a pair X.sub. k, Y.sub.k that is a good approximation, but where neither M.sub.k nor P. sub.k is too large for the dividers, and then using diophantine calculation methods and a further equation relating to the way the PLL's signals are combined, to calculate N.sub.k and Q.sub.k. The integers M. sub.k, N.sub.k, P.sub.k, and Q.sub.k are then used to program the four dividers. Several forms of the invention further use a controlled reference source, and by varying F.sub.refj, allow more than one approximation to be made, and the error for each to be determined. After several such calculations, a low error one is chosen, and its M.sub.i, N. sub.i, P.sub.i and Q.sub.i values used. The invention works with synthesizers where the PLL's signals are combined to produce F.sub.out, and with synthesizers where the combined signal is used as a feedback signal for the PLL's.