2-D discrete cosine transform circuit with reduced number of multipliers

摘要

An image data processing apparatus includes a v calculating block 7 for calculating a vector v from a vector x which has 64 elements in a real space and which has been generated as a sequence of image data in 8 rows and 8 columns in the real space, a w calculating block 8 for calculating a vector w from the vector x in the real space, and a c calculating block 9 for adding and subtracting elements of the vector v and elements of the vector w , thereby producing a vector c which has 64 elements in a space of spatial frequencies. The elements of the vector c in the space of spatial frequencies are arranged into data in 8 rows and 8 columns in the space of spatial frequencies.