2-D DISCRETE COSINE TRANSFORM CIRCUIT WITH REDUCED NUMBER OF MULTIPLIERS

摘要

The present invention relates to a computing device suitable for use in the calculation of two-dimensional discrete cosine transform (DCT) or inverse discrete cosine transform (IDCT). Conventional DCT computation circuit and IDCT computation circuit have an unreasonable point in the overall circuit size, and in the conventional two-dimensional DCT computation circuit (the IDCT computation circuit is also the same), the first computation circuit 1 and the second computation circuit 3 Since the multiplication is performed twice in the RTI ID = 0.0 ;Accordingly, in order to solve the above problem, the present invention arranges the image data of 8 rows x 8 rows in the real space in a predetermined order so as to form a vector x in 64 real spaces. A v calculation block for calculating the vector v from the vector x in the real space, a w calculation block for calculating the vector w from the vector x in the real space, and the vector and a c calculation block for calculating the number of elements 64 on 64 frequency spaces by adding and subtracting the components of v and the components of the vector w. The present invention relates to an arithmetic unit that allows two-dimensional DCT operations to be performed by using a smaller number of multipliers by rearranging and obtaining eight rows by eight columns of data in the frequency space.