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Parallel adding circuit using 3amp;times;3 matrix of .+-. quinary number representation
Parallel adding circuit using 3amp;times;3 matrix of .+-. quinary number representation
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机译:使用。+-的3×3矩阵的并行加法电路。五进制数表示
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摘要
A parallel adding circuit using a quinary number representation including a register having a sign bit, numeral bits and a special bit. The sign bit equal to 1 indicates positive and sign bit equal to 0 indicates negative. The numeral bits includes a first, second and third bits representing weights of 3, 2 and 1, respectively. The special bit is formed by a logical AND of an inverse (logical NOT) of said second bit and an inverse (logical NOT) of said third bit.
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