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DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts
DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts
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机译:DMA控制器使用可编程定时器,传输计数器和或逻辑门控制数据传输中断
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摘要
A DMA controller interrupts data transfer as needed to transfer the bus use permit to the CPU and resumes data transfer when the CPU completes the memory use in the burst mode in which the predetermined number of words is transferred between the I/O device and the memory.
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