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Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems
Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems
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机译:单相时钟分配电路,用于向多个芯片集成电路系统提供时钟信号
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摘要
A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.
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