Circuit for generating a stretched clock signal by one period or one-half period

摘要

The time a microprocessor CPU must wait for memory access is controlled to be one of two values by stretching the CPU clock signal either a first time duration or a second time duration, depending on the expected delay caused by the memory access. The clock stretching is in increments of one quarter of the CPU clock period and is done with both the leading and trailing edges of the clock pulse.