Direct memory access control device for use with a single n-bit bus with MOF the n-bits reserved for control signals and (n-m) bits reserved for data addresses

摘要

A DMA control device (10) is connected with an n-bit address bus (12) by way of a bidirectional internal n-bit bus (14). The m most significant bits of signals received on the bidirectional bus (14) are reserved for carrying codes which identify or enable the DMA device to respond, to generate a load signal, to generate a count signal, and to generate an output signal. The remaining bits are reserved for address data. The load signal causes the remaining bit addresses to be loaded into counters (22) or registers (40). The count signal causes the counters (22) or a latched incrementor (44) to increment. The output signal controls three-state buffers (24, 42, 46) which cause the current address to be outputted on the bidirectional bus. In this manner, the DMA control device has only a single bus and in the embodiment of FIG. 2 replaces the counter array with a register array.