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Reducing stall delay in pipelined computer system using queue between pipeline stages
Reducing stall delay in pipelined computer system using queue between pipeline stages
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机译:使用流水线级之间的队列减少流水线计算机系统中的停顿延迟
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摘要
A pipelined computer system employs a queue stage to receive the output of one pipeline stage when a stall occurs in the next stage or downstream of the next stage. This avoids stalling earlier stages of the pipeline. Subsequently, the pipeline advances through the queue, until a bubble occurs. When a bubble is subsequently generated upstream and enters the queue stage, a multiplexer switches the input of the next stage to receive the output of the one stage instead of from the queue stage, and the content of the queue is overwritten. By this mechanism, the delays inherent in processing branches can be reduced.
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