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Decimation filter for a sigma-delta converter and data circuit terminating equipment including the same
Decimation filter for a sigma-delta converter and data circuit terminating equipment including the same
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机译:用于sigma-delta转换器的抽取滤波器和包括该抽取滤波器的数据电路终端设备
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摘要
A decimation filter for converting a received train of sigma- delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples having a PCM clock in accordance with the formula ##EQU1## includes a computer for computing one PCM sample from a sequence of sigma-delta samples in synchronism with the PCM clock and also a comparison circuit for determining whether phase correction of the PCM clock is necessary to lock the generation of the PCM samples on the sigma-delta clock extracted from the received sigma-delta signal, the decimation filter including shifters which shift the computation process at least one sigma-delta clock pulse in order to provide phase control in the generation of the PCM samples.
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