Digital signal processor with delayed-evaluation array multipliers and low-power memory addressing

摘要

A digital signal processor including a digital FIR filter and memory for storing filter coefficients operates at a reduced power level by using array multipliers that calculate partial products only when the partial products in a preceding row of the array have stabilized. The dynamic CMOS adder arrays in each multiplier are triggered to perform their evaluations only after predetermined time periods have elapsed, which are sufficient to permit the preceding row to stabilize. Coefficients are addressed from the memory using low-power addressing circuits, such as a Gray code counter or a one-bit wide circular shift register, so that the overall digital signal processor consumes a reduced amount of power during memory addressing.