Choice manner of retiming signal, selection manner and retiming signal generation device null of retiming

摘要

PURPOSE: To realize accurate data retiming by selecting a retiming signal for a received serial data stream from plural local clock signals different in phase. CONSTITUTION: The indications of approximate time positions of data edge transitions related to DPLL local clocks, generated by a generator 14 are transferred from a data edge sorting circuit 30 in a digital phase-locked loop front end circuit 15 to the corresponding number of time slot counters 32 in a circuit 20 through a line 19. This counter block 32 includes a total counter and outputs a signal to a clock selecting logic 38 through a line 35. When a predetermined number of data transitions occur, that is, when they are counted by time slot counters, the total counter instructs this.