Device null in order to make the parasitic junction capacitance of the insulating collector lengthwise PNP transistor

• 1. 一种自由集电极纵向PNP管及其制备方法 [P] . 中国专利： CN106449740A . 2017-02-22
• 2. 悬浮集电极PNP集成电路晶体管及其制作方法 [P] . 中国专利： CN105529361B . 2018.12.04
• 3. APPARATUS FOR MINIMIZE PARASITIC JUNCTION CAPACITOR OF INSULATED COLLECTOR VERTICAL PNP TRANSISTOR [P] . 日本专利： JPS62126704A . 1987-06-09

  机译： 最小化绝缘集电极垂直PNP晶体管寄生结电容器的装置

• 4. Device for minimizing parasitic junction capacitances in an insulated collector vertical P-N-P transistor [P] . 美国专利： US4935796A . 1990-06-19

  机译： 使绝缘的集电极垂直P-N-P晶体管的寄生结电容最小的装置

• 5. A DEVICE FOR MINIMIZING PARASITIC JUNCTION CAPACITANCES IN AN INSULATED COLLECTOR VERTICAL P-N-P TRANSISTOR [P] . 英国专利： GB2183415B . 1990-04-11

  机译： 用于最小化绝缘集电极垂直P-N-P晶体管的寄生结电容的装置

• 1. High performance 0.1μm CMOS device with suppressed parasitic junction capacitance and junction leakage current [C] . Hyun Sik Kim, Shiang Yang Ong, Manju Sarkar, European solid-state device research conference . 2002
• 2. Separating Radiation and Thermal Effects on Lateral PNP Bipolar Junction Transistors Operating in the Space Environment. [D] . Campola, Michael J. 2011
• 3. Capacitance Variation Induced by Microfluidic Two-Phase Flow across Insulated Interdigital Electrodes in Lab-On-Chip Devices [O] . Tao Dong, Cátia Barbosa 2015
• 4. A high-frequency GaInP/GaAs heterojunction bipolar transistor with reduced base-collector capacitance using a selective buried sub-collector [O] . Yang YF, Yang ES, Ou HJ, 1996
• 5. Method for the Fabrication of Dielectric Isolated Junction Field Effect Transistor and PNP Transistor. [R] . Cunniff, K. F. 1983

• 1. 一种3um P阱CMOS兼容纵向PNP晶体管β的研究 [C] . 谭开洲 ,司琴 ,李儒章 . 中国电子学会第八届青年学术年会暨中国电子学会青年工作委员会成立十周年学术研讨会 . 2002