首页> 外国专利> METHOD FOR SYNCHRONIZING FIRST FRAME SET CORRESPONDING TO FIRST PROCESSOR WITH SECOND FRAME SET CORRESPONDING TO SECOND PROCESSOR AND COMPUTER DEVICE

METHOD FOR SYNCHRONIZING FIRST FRAME SET CORRESPONDING TO FIRST PROCESSOR WITH SECOND FRAME SET CORRESPONDING TO SECOND PROCESSOR AND COMPUTER DEVICE

机译:与对应于第二处理器和计算机设备的第二框架集同步对应于第一处理器的第一框架集的方法

摘要

PURPOSE: To synchronize the frame of one or plural slave processors with the frame of a master processor and to synchronize an input data sample with an output data sample by realizing a phase register. ;CONSTITUTION: A processor 400 is constituted of a digital signal processor 410, and DSP 410 is driven by a DSP clock 411. A processing system 401 is connected to a sound signal DMA circuit 401 and the DMA circuit 401 facilitates the transfer of information with at least either a local memory 412 or a bus 450. A bus controller 440 connected to DSP 410 and a bus interface circuit 403 facilitating communication between a processor 401 and the bus 450 are provided furthermore. The bus 450 can be set to a computer bus to which the processor 404 can be connected or a host bus connected to the host processor 460.;COPYRIGHT: (C)1994,JPO
机译:目的:使一个或多个从处理器的帧与主处理器的帧同步,并通过实现相位寄存器来使输入数据样本与输出数据样本同步。组成:处理器400由数字信号处理器410组成,DSP 410由DSP时钟411驱动。处理系统401连接到声音信号DMA电路401,而DMA电路401通过至少一个本地存储器412或总线450。还提供了连接到DSP 410的总线控制器440和促进处理器401与总线450之间的通信的总线接口电路403。总线450可以设置为可以将处理器404连接到的计算机总线,或者可以设置为连接到主处理器460的主机总线。版权所有:(C)1994,JPO

著录项

  • 公开/公告号JPH06318189A

    专利类型

  • 公开/公告日1994-11-15

    原文格式PDF

  • 申请/专利权人 APPLE COMPUTER INC;

    申请/专利号JP19930132370

  • 发明设计人 ANDERSON ERIC C;

    申请日1993-05-12

  • 分类号G06F15/16;

  • 国家 JP

  • 入库时间 2022-08-22 04:23:58

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