CMOS LOGICAL SIGNAL TRANSMISSION BETWEEN VERY LOW-VOLTAGE CHIPS FOR MANY HIGH-SPEED OUTPUT LINES RESPECTIVELY RELATED TO LARGE CAPACITIVE LOADS

摘要

PURPOSE: To provide a CMOS device which can be dramatically reduced in dynamic power consumption and has signal transmission between very low- voltage chips. ;CONSTITUTION: A CMOS integrated circuit(IC) device is provided with internal logic circuits 28, 34, and 40 of the conventional type which operate at an internal logic level of 3.3 V or 5 V, output buffers 30, 36, and 42 which convert the internal logic level into an external logic level of 0.3 V, and input buffers 26, 32, and 38 which convert the external logic level of 0.3 V into the internal logic level. In the CMOS IC device containing many external output loads which are driven at very high clock speeds and have relatively high capacity values, electrostatic discharge(ESD) protection matter can be included in all signal inputs and outputs of the IC device by setting external logic level to the low level. The ESD protection matter is provided with a pair of silicon P-N junction type diodes connected in parallel between each signal line and a grounding reference and having opposite polarities.;COPYRIGHT: (C)1995,JPO