Bistable memory cells 40 are coupled to read bit lines 51-54 through transistors 55-58 controlled by word lines 300, 310. Additional (write) lines 22-25 are coupled to the cells and isolated from the bit lines. During a read-modify-write operation precharge on the bit lines after the read operation is undisturbed when writing occurs into the cell from the write lines since word lines 300, 310 are now low. In the dual port memory a conflict determining circuit is used to provide a predetermined state to the cell when simultaneous access is sought for writing to the cells with conflicting data. IMAGE
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