Symmetrical Multi-Layer Metal Logic Array with Continuous Substrate Taps and Extension Portions for Increased Gate Density

摘要

A gate array architecture is disclosed that utilizessignificantly less silicon area than the prior art. The core cellincludes a four transistor arrangement in which a substrate tap islocated adjacent to the transistor pair. This provides for a more"symmetric" cell array than those in the prior art. Through theplacement of the taps outside of the transistors the power lineconnections can be routed in a simple and efficient manner. Thearchitecture includes an extension portion in the contact region ofthe cell to further reduce wiring complexity. In addition the gatearray architecture mirrors pairs of transistor columns to allow forthe sharing of substrate taps between pairs of columns. Thismirroring feature further reduces routing complexity.