首页>
外国专利>
Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
展开▼
机译:具有连续衬底抽头和延伸部分的对称多层金属逻辑阵列,可提高栅极密度
展开▼
页面导航
摘要
著录项
相似文献
摘要
A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.
展开▼