High Current High Voltage Vertical PMOS in Ultra High Voltage CMOS

摘要

A vertical transistor which is built in a substrate of a given first carrier type utilizing standard processes but which has a unique layout which facilitates high voltage, high current operation while still conserving space. The transistor is built utilizing a repeatable combination gate/source area that is built in the upper area of the substrate such that the remaining lower portion of the substrate underneath the combination gate/source area is the drain area of the transistor.