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Self-timed real-time data transfer in video-ram
Self-timed real-time data transfer in video-ram
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机译:视频RAM中的自定时实时数据传输
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摘要
A Video-RAM semiconductor memory device comprised of a RAM array having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulus such as a RAS clock from an external controller indicating a coarse timing location for a data transfer between the RAM array and the serial access array. The control logic then provides control signals, that are internally synchronized with a serial clock, and that occur during a period that a tap pointer is equal to a value one less than a programmable target value or an input target address. This causes a row in the RAM array corresponding to an input row address to be transferred between the RAM array and the serial access array.
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