Improved VGA controller with frame buffer memory arithmetic and method the

摘要

An improved VGA controller 10 with arithmetic logic 24 and the method are provided to increase system performance with efficient minimum use of the required bus bandwidth. The controller 10 includes a bus 18 for the frame buffer 14 in which the system CPU 12 or the display controller 16 is accessed and controlled. The display controller 16 includes a display FIFO 28 for storing display data from the frame buffer 14 to be used for the display controller 16. This display FIFO 28 coupled with the arithmetic logic 24 causes the display controller 16 to continue outputting the display data even when the system CPU 12 is accessing the display data of the frame buffer 14. [ The arithmetic logic 24 allows the display FIFO 28 to be kept at the maximum possible size to allow for a bus request by the system CPU 12 immediately.