Multichannel (CH) synchronous circuits in digital signal processors (DSPs)

摘要

A digisignal processor (DSP) for receiving the inter-station relay signal and the subscriber DTMF signal to determine the presence or absence of the signal and determining the signal type in the digielectronic switching system receives the 32-channel PCM data, A DSP channel designation for confirming which channel is the first channel to be processed by the digisignal processor when signal processing for a plurality of channels is performed, /RTI ;The present invention resides in that the status display output signals XF0 to XF3 of the DSPs 1 to 4 are input to the data input terminal D and the reset terminal and are retimed, A plurality of D flip-flops (11-14) for providing as a signal; And receives the frame synchronizing signal Fs to be delayed in synchronization with the inverse signal / CLK of the clock and the frequency dividing clock of one channel period provided by the counter 7 and the inverse signals SQ2 and / SQ2 thereof (40) for providing different clock signals to the clock terminals of the plurality of D flip-flops (11-14), so that the digisignal processor (DSP) can correctly process the channel information in any situation .