Data parallel processor in video decoder

摘要

The present invention relates to an apparatus for parallel processing data using shift registers and counters, and a data distributing means for distributing data of an input bit stream to a module buffer comprises: A slice start code, and a slice vertical position in input data from a shift register unit, and based on this detection information, a plurality of pieces of input data And a local register for storing the count value generated in the counter unit according to the control signal of the control unit, and a local register for storing the count value generated in the counter unit according to the control signal of the control unit. And a control unit for controlling the car stored in the local register unit And a latch unit for latching data to be transferred from the shift register unit to the plurality of module buffers in accordance with a latch clock signal from the control unit , The value of the counter is stored in the register and then reloaded, thereby preventing the transmission error of the data.