An apparatus for the correction of simple bit errors and for the recognition of double bit errors in the case of data transmission.

摘要

An apparatus which corrects single bit errors and detects double bit errors including an encoder/decoder. During encoding the encoder/decoder produces a plurality of parity bits. These parity bits allow the correction of single bit errors in transmission. The encoder/decoder includes a plurality of arrays. Each array consists of logic gates arranged in the form of a binary tree. When the encoder/decoder is used in decoding, the encoder/decoder produces a plurality of syndrome bits. These syndrome bits are used to correct single bit errors in transmission. Error correction circuitry composed of logic gates receive the syndrome bits and generate flipper bits used in error correction. When a first data bit for which a first flipper bit is being generated is used in the production of a majority of syndrome bits, a logic gate which generates the first flipper bit receives as input only syndrome bits in the production of which the first data bit was used. When a second data bit for which a second flipper bit is being generated was not used in the production of a majority of syndrome bits, a logic gate which generates the second flipper bit receives as input only syndrome bits for the production of which the second data bit was not used.